Implementation of 8-Bit Asynchronous SAR ADC

This study analyses the design of SAR ADC that is suitable for implementing in low power applications. The designed SAR ADC minimizes the complexities associated with its design using higher frequencies by avoiding the usage of oversampled clock. A Bootstrap circuit is designed for a sampling and holding which improves increased linearity. Another aspect of the low power is designing a comparator such that it does not require a pre-amplifier. Successive Approximation register (SAR) ADC is implemented using a charge redistribution DAC. The SAR logic block generates the digital code thus reducing power consumption in the circuits. Hence, an 8-bit SAR ADC that exhibits a maximum sampling frequency of 20MHz using 250 nm CMOS technology is designed in S-SDIT Tanner and its working is verified through circuit level simulations.