Fault-Resilient Brent-Kung Adder Design Using Advanced Built-in Self-Test (BIST) Architecture

In modern digital systems, ensuring both high performance and reliability is essential, especially in fault-sensitive environments. This research introduces the design and implementation of a fault-tolerant Brent-Kung adder, integrated with an advanced Built-In Self-Test (BIST) framework. The Brent-Kung adder, known for its efficient carry propagation and speed optimization, is augmented with BIST techniques to enhance its reliability and testability in digital systems. A Linear Feedback Shift Register (LFSR) is used to produce pseudo-random test patterns, while a Multiple Input Signature Register (MISR) compresses the adder’s output into a compact signature for fault detection. The design is carried out in Verilog and synthesized using Xilinx Vivado 2019.1 to evaluate performance metrics, including area utilization, speed, and fault coverage. By combining the Brent-Kung adder's high-speed characteristics with a robust BIST framework, the research achieves an effective balance between performance and fault detection. This approach provides a promising solution for applications that require both computational efficiency and increased reliability in fault-sensitive environments.