Implementation of 256-Bit AES and SHA3 on FPGA

The work discusses an implementation of the SHA3 algorithm and AES encryption/decryption algorithms which is of 256 bits using Verilog HDL on FPGA. The approach emphasizes optimizing resource utilization and minimizing latency through advanced pipeline design and parallel processing techniques. It provides detailed insights into design considerations, algorithmic intricacies, and FPGA-specific optimizations, demonstrating high-speed operations with minimal overhead. Additionally, the work justifies the synergistic application of both algorithms, leveraging their complementary strengths to offer a comprehensive and efficient solution for secure data processing in real-time applications. It contributes significantly to the advancement of cryptographic systems by providing a robust framework for secure and responsive data handling in modern computing environments. Anticipated work provides a straightforward implementation, suitable for swift deployment in real-world settings. Able to achieve usage of 8271 LUTs using Sha-3 function and achieve 170.94 Mhz frequency which is greatly reduced from 245Mhs when used with AES algorithm with efficient LUT usage.