Design of High Efficiency Power Amplifier Using LDMOS Technology for RF Transmitter System

This paper discusses the design, construction, and evaluation of a high-efficiency 2.4 GHz power amplifier (PA) utilizing harmonic suppression through discrete circuit technology. The PA is built using Laterally Diffused Metal-Oxide Semiconductor (LDMOS) technology. The amplifier achieves a peak power-added efficiency (PAE) of 48.6%, delivering an output power of 40 dBm with a power gain of 15.7 dB. The input and output reverse losses are measured at -8.7 dB and 4.4 dB, respectively. The experimental of PA prototype features compact dimensions ($68 \times 36 \mathrm{~mm}$) and provides a high output power of 10W, outperforming other RF amplifier technologies.