A 132GHz Frequency Tripler in 65-nm CMOS with Low Power Consumption
A 132GHz frequency tripler in 65-nm CMOS with low power consumption is proposed in this paper. The design includes a balanced frequency tripler and two driving amplifier(DA). This design integrates transformer and current reuse structures in the inter-stage matching between the frequency tripler and the driving amplifier, significantly decreasing DC power consumption. The 3dB bandwidth of the tripler is $123.3 \mathrm{GHz} \sim 139.2 \mathrm{GHz}(12.11 \%)$, the peak conversion gain(CG) is 2.1 dB at 132GHz and the harmonic rejection ratio in operating band is higher than 35dBc.The frequency tripler consumes 19.9 mW DC power, and the size of the chip is $0.12 \mathrm{mm}^{2}$.
Authors
- Qingfeng Zhang (ORCID: https://orcid.org/0000-0002-7779-6495)
- Yinian Feng (ORCID: https://orcid.org/0000-0002-8419-5436)
- Kai Kang (ORCID: https://orcid.org/0000-0001-9044-6249)
- Mingyang Ji (ORCID: https://orcid.org/0000-0001-6462-0709)
- Bo Zhang (ORCID: https://orcid.org/0000-0003-1288-1549)
- Gang Yang (ORCID: https://orcid.org/0000-0002-2418-3820)
Institutions
- University of Electronic Science and Technology of China (CN)
Publication Details
- Published
- 2024-09-22
- DOI
- https://doi.org/10.1109/apcap62011.2024.10881575
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- China Postdoctoral Science Foundation