Azimuth Pre-filtering Implemented in FPGA Based on Multi-phase Decomposition

Azimuth pre-filtering is usually used to address the redundancy issue in Synthetic Aperture Radar (SAR) raw echo data, and reduce data size while improving the Signal-to-Noise Ratio (SNR). An azimuth pre-filtering method based on multi-phase decomposition for FPGA implementation is proposed in this paper. Firstly, a multi-phase decomposition-based Finite Impulse Response (FIR) decimation filter is derived for filtering and extraction through dividing the filter into multiple sub-filters. Then, the implementation process of the above-mentioned filter is designed for FPGA, and the module framework is provided. Finally, experimental results are given to demonstrate the correctness and effectiveness of the proposed method.