Design and Implementation of Partially Parallel LDPC Decoder for Low Earth Orbit Micro-Nano Satellites Data Transmission

This paper proposes a LDPC decoder for Low Orbit Micro-Nano Satellites Date Transmision. By analyzing the H-matrix characteristic, each cyclic sub matrix of the H-matrix is mapped to a Ramdom Access Memory(RAM). The address and data lines of the RAM are fully utilized to realize that RAM can be represented as both an H -matrix and an information storage matrix. The results on FPGA platform show that when the Eb/N0 is 4dB, the throughput of the decoder reaches 145Mbps, which improves the margin of data transmission links and meets the demand for data transmission. The decoder has completed in orbit verification on the experiment verification satellites.