Impact of Gate/Drain Biases in FDSOI-Based Analog Synapse on Artificial Neural-Network Performance

In this work, a low-cost artificial intelligent analog synapse using commercial 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS technology was applied in a computing-in-memory (CIM)-based neural network (NN) and co-optimized from the device level to the system level. Through read-and-write scheme optimization, the synapse realized the nonlinearity of 0.14/0.90 and the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {Pot}.}$ </tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {Dep}.}$ </tex-math></inline-formula> ratio of 4.3:1, as well as excellent retention and uniformity. The comprehensive performance of the CIM-based NN system, including accuracy, energy, and latency, was evaluated by the open-source simulation tool NeuroSim+. Based on the device and system co-optimization, the CIM-based NN system can achieve an accuracy of 92% and energy consumption of only 0.45 mJ during online training. This work revealed the feasibility of the FDSOI FET-based synapse as a high performance and low cost solution for the CIM-based NN system.