A 34.8–40.8-GHz Dual-Mode Fast Relock Linear FMCW Frequency Synthesizer

This article presents a 34.8–40.8-GHz dual-mode energy-efficient linear and fast relock frequency-modulated continuous-wave (FMCW) frequency synthesizer in 28-nm CMOS for low-power, high-efficiency, high-range-resolution and comprehensive-range FMCW radars. Fast frequency-modulated (FFM) and regular frequency-modulated (RFM) modes are proposed to generate linear chirp signals with different slopes for different application scenarios. Two-point modulation (TPM) and cycle-slipping-restraint (CSR) techniques are explored in the FFM mode and RFM mode, respectively, to reduce the idle time (T_idle) and improve the efficiency of the radars. In the FFM mode, an optimal nonlinearity digital predistortion (NDPD) scheme based on a linear interpolation algorithm is proposed to minimize the memory of lookup tables (LUTs) and limit the nonlinear error of frequency-modulated path to less than 1 MHz. The system expends 75.9-mW power to deliver a 248-MHz/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>s chirp slope with a 3-MHz root-mean-square frequency-modulated (rms-FM) error over a 6-GHz bandwidth. In the RFM mode, only a fractional-N charge pump phase-locked loop (CP-PLL) is employed to generate a slow but linear chirp signal, reducing power consumption by 34.5% compared with the FFM mode. The CSR technology is explored to reduce the relock (transition from highest to lowest frequency) time in sawtooth chirp generation, achieving a chirp slope of 2–6 MHz/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>s with rms-FM error of 153 kHz and enhancing the relock speed by 3–14 times.