An Equivalent Circuit Model of 12 nm P-FinFET for NBTI Effect

A negative bias temperature instability (NBTI) equivalent circuit model based on P-FinFET of a 12nm CMOS PDK and electrical components and arithmetic units of EDA software is presented. The P-FinFET circuit model consists of electrical components such as voltage sources, controlled sources, adders and multipliers, and other arithmetic units. The model is set up with five tunable input parameters, including stress time, gate width, gate length, process corner (slow/ fast/ typical), and temperature. The equivalent circuit model also takes into account bias conditions of transistor, such as gate-source voltage, drain source voltage, and drain gate voltage, which will affect NBTI. Simulation result shows that the degradation curves of the equivalent circuit model for P-FinFET are in concordance with experimental data presented in previously published literatures.