Multifaceted impacts of reliability issues: trap dynamics, positive bias temperature instability, and effect of temperature on the HSSP-nTFET

Abstract This study investigates the influence of interface trap charges (ITCs) on the performance parameters of the proposed lateral hetero-stacked source with pocket n-type tunneling field-effect transistor (HSSP-nTFET). The influence of different concentrations of donor and acceptor trap charges on the device’s DC performance metrics is thoroughly examined. It is observed that the presence of interface traps in the device leads to variations in both the threshold voltage ( V th ) and subthreshold swing (SS). To evaluate the impact of various ITCs on analog / RF performance, critical parameters including electric field characteristics, Transconductance ( g m ), parasitic capacitance, cut-off frequency ( f T ), gain-bandwidth product, transit delay, TFP, R out and device efficiency have been comprehensively analyzed for the HSSP-nTFET. Additionally, this work investigates the reliability of the proposed device by analyzing its susceptibility to interface trap conditions, temperature variations (280 to 480 k), and also, positive biased temperature instability induced degradation, as inspected in this study, poses significant reliability concerns for analog/digital circuit design, necessitating careful consideration and mitigation strategies. Vital statistics yielded in this 3D simulation research are on-current ( I ON = 8.18E −5 A μ m −1 ), off-current ( I OFF = 1.33E −19 A μ m −1 ), V th = 0.18 V, SS avg = 14 mV dec −1 , g m = 1.86E −4 S and f T = 0.384 THz which can serve as a strong contender for energy-efficient and high-performance applications.