Analytical modeling of a 3D inductor based on a through silicon via and an LC voltage-controlled oscillator with a core area of 0.08 mm²

Abstract Through-silicon via (TSV) technology has shown promising potential in reducing die area and enhancing the quality factor of three-dimensional (3D) inductors on a chip. An efficient method for rapidly establishing a TSV inductor model is proposed. It takes the excess internal inductance of the redistribution layer into account and an algorithm is developed to rectify errors arising from current changes in the conductor. The iteration time of the proposed method is about 60 ms and it has been verified by an electromagnetic simulator, demonstrating a maximum error of less than 1.5% across multiple parameter arrays. Moreover, a voltage-controlled oscillator (VCO) with inductors and capacitors based on TSV technology is introduced. The prototype is implemented in a standard 180 nm complementary metal–oxide semiconductor process. The VCO operates in the frequency range between 2.17 and 2.35 GHz, with a core area of only 0.08 mm 2 , and the phase noise at 1 MHz offset is about −129.2 dBc Hz −1 .