Boot process of RISC-V multi-core heterogeneous SoC integrated with eFPGA

The RISC-V multi-core heterogeneous SOC has five harts that divided into three clusters, and integrates an eFPGA. Inter-cluster is asymmetric-multiprocessor and intra-cluster is symmetric-multiprocessor. The SoC not only has the powerful computing ability of general CPU, but also has the scalability and parallel processing ability of FPGA. But it also makes the process of loading and launching the firmware extremely complicated. According to the hardware architecture of SoC and possible use scenarios, four basic bare-metal and operating system combination boot schemes and three methods to load eFPGA executable files are designed. The actual test shows that the boot process can work as expected. These boot schemes cover almost all the usage scenario of SoC, expand the application range of SoC, and are more conducive to the popularization and use of SoC.