Nonvolatile Organic Floating-Gate Memory Using N2200 as Charge-Trapping Layer

In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 103.

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Publication Details

Journal
Applied Sciences
Published
2025-02-20
DOI
https://doi.org/10.3390/app15052278
Citations
1
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.73

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Nonvolatile Organic Floating-Gate Memory Using N2200 as Charge-Trapping Layer

Hu Liu, Mengqi Ma, Wenting Zhang, Shuang Li et al.
1 citations
Applied Sciences
Advanced Memory and Neural Computing
0.73
article

Nonvolatile Organic Floating-Gate Memory Using N2200 as Charge-Trapping Layer

Hu Liu, Mengqi Ma, Wenting Zhang, Shuang Li, Jia-Chen Shang, Ma Dong-Ping
article en
1 citations

Abstract

In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 103.

Applied SciencesVol. 15(5)
Lanzhou Jiaotong University (CN)
National Natural Science Foundation of China, Natural Science Foundation of Gansu Province
Openalex Percentile: Top 31%
Advanced Memory and Neural Computing
0.73
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