Comparative Analysis of Heterogeneous Adders: Evaluating Performance across 12-bit, 14-bit, and 16-bit Configurations

Abstract Digital Signal Processing (DSP) heavily relies on repetitive addition and multiplication operations, making adders a crucial component in DSP systems. Likewise, in processor design, an efficient adder circuit is essential for optimizing compactness, achieving high speed, and minimizing power consumption, particularly when utilizing Xilinx technology. This study delves into the exploration and design of an effective adder architecture by examining various parallel, synchronous adders and proposing a novel combination. The presented research introduces heterogeneous adders composed of concatenated homogeneous sub-adders such as Ripple Carry Adder (RCA) and Carry Look Ahead Adder (CLA), which is implemented by using VIVADO 2017.1. The comprehensive assessment involves simulation, synthesis, and Register-Transfer Level (RTL) implementation to generate utilization and power reports. Specifically, this paper focuses on the design of 12-bit, 14-bit, and 16-bit heterogeneous adders. Through a thorough analysis, power consumption and area utilization are scrutinized and compared across each model. The combination of 4-bit RCA + 8-bit CLA, 10-bit RCA + 4-bit CLA, and 4-bit RCA + 12-bit CLA provide the least total on-chip power consumption of 8.141 W, 9.482 W, and 10.827 W in 12-bit, 14-bit and 16-bit heterogeneous adders respectively. Similarly, 6-bit RCA + 6-bit CLA, 6-bit RCA + 8-bit CLA, and 6-bit RCA + 10-bit CLA provides less area utilization. The goal is to identify the model exhibiting the least power consumption and optimal area utilization, contributing to the advancement of efficient adder circuits for DSP systems and processor designs.