A DL-Mesh and dual check based multi-core chiplet communication mechanism

As transistors continue to shrink, chip designs become increasingly complex and densely packed, presenting a challenge in balancing performance and cost. That motivates designers to divide SoC into many small specialized chips (chiplets) with maximum performance benefits but lower complexity and cost. We focus on communication algorithm of chiplets and propose a dual layer Mesh topology and an adaptive congestion fault-tolerant routing algorithm, which achieve a greater throughput than mesh topology. Besides, we propose two dual check mechanism for soft error in communication, it can detect single bit and double bits errors 100%. The 2*2 and 3*3 multi-core architectures (based on our topology and check mechanism) only decreases performance by about 7% -11%, and 35% -48% under single and double node failures.