A Short Survey of Truncated Multipliers

As the world of digitalization continues to advance, extensive research has led to significant developments in the use of truncated multipliers. While traditional full-width multipliers were used in all applications, there are specific cases where truncated multipliers were adopted, albeit with some loss of accuracy. This shift sparked considerable research in the field. Truncation focuses on only considering the carries generated during the final result calculation, ignoring the least significant columns of the full-width multiplier. Over the years, numerous studies have explored ways to reduce circuitry by truncating the least significant bits (LSB) using combinations of AND and OR gates, all while aiming to minimize errors, reduce delays, and cut down power consumption. This study provides a detailed analysis of research on Baugh-Wooley architecture-based truncated multipliers from 1973 to 2024, offering a comprehensive review of decades of efforts to create smaller, more efficient multipliers.