Laboratory Experiments for Introductory and Advanced VLSI Courses

This paper focuses on the experimental design of large scale integrated circuits (LSICs) by senior and graduate level students at Missouri University of Science and Technology.We have designed a series of experiments to teach fundamentals of full-custom IC design, which include front-end to back-end flow.These labs help IC beginners understand the entire full-custom design process.Labs are executed in both an undergraduate and advanced graduate course.The lab experience includes projects.An example project -a 100 MHz output clock phase-lock loop (PLL) with 10 MHz input -will be discussed.In this lab, students use Virtuoso schematic editor to develop each portion of the PLL: the phase detector, charge pump, filter, voltage controlled oscillator, and a divider.The sizes of FETs are determined based on simulation results.Three kinds of divider structures are tested to find the one which provides the best performance.After the design passes front-end simulation, the students implement the layout of these modules in the layout editor, and DRC and LVS are executed to verify their design.Finally, post-simulation is used to prove the PLL works well in a long time simulation in the presence of layout parasitics and noise.Completion of these labs significantly improves the students' understanding of the basic full-custom design flow.