Results of Validation Analysis for Multi-Memory Bus BIST Engines

Currently, most of digital IPs which are used in SoCs including test and monitoring systems, are implemented in a form of flexible macros which can be configured for the specific proposes. For the validation and quality assurance (QA) of these IPs both specific to these IPs' properties, and general methods of validation and QA should be used. Built-in self-test and repair solutions (BIST) which address IC reliability issues, need to be properly validated and assured quality wise. A wrongly generated or configured BIST engine may miss some system faults. The validation problems are getting complicated for the engines with numerous configuration parameters which can be dynamically changed. A specific such case - a multi-memory bus BIST engine (MMB-BE) is considered. The results on MMB-BE validation are presented including modifications in QA flow and MMB-BIST itself.