A High-Speed and Low-Power STT-MRAM with Complementary Symmetric Reference Read Scheme

STT-MRAM is gradually becoming a general-purpose memory by virtue of its non-volatile and low-power characteristics. In this paper, we propose a read scheme for STT-MRAM based on 55nm CMOS process, which combines CSR architecture and double-tail dynamic comparator. This design incorporates 128 data cells and a reference cell per bit line, ensuring optimal impedance matching and effectively reduces the circuit area. Simulation results indicate that this scheme achieves a read delay of 2.2ns at IV supply voltage for a 256-bit STT-MRAM, with a read energy consumption of 196fJ. The layout area is about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.016\ \text{mm}^{2}$</tex>.