Aging Protected Precision CMOS Current Reference with Process, Supply Voltage and Temperature Compensation

A mathematical model has been developed describing the operation of current source achieving current variation that is less than 1-2% from the nominal value. A circuit implementation for the derived equations is presented. Shortcomings of the architecture implemented using lvt only devices are described, and a solution is proposed. The proposed technique demonstrates a substantial reduction in degradation, outperforming previous methods by 36%. This significant improvement is a result of the comprehensive approach to mitigating transistor aging effects, incorporating advanced modeling and simulation techniques, as well as innovative circuit design methodologies. The technique is relevant for modern 5nm and below technology nodes. SPICE analysis performed over the designed circuit shown less than ± 4% variation of the reference current in the -40..1250C temperature range considering the process variations in ±3 sigma range.