A PLL-Less Direct Deadbeat Control for APF Under Online Inductance Identification
The slow dynamic characteristics of the phase-locked loop (PLL) in traditional APF control algorithms affect the transient and steady-state performance of inverters. Therefore, a PLL-less direct deadbeat control method is proposed in this paper. Compared with the advanced dual-loop composite control strategy with phase-locked loop based on PI and repetitive control (PIRC), the proposed method achieves faster dynamic control capability and a higher harmonic compensation rate, all without the need for a phase-locked loop, load current sensor, or APF current sensor. Additionally, real-time online identification of the equivalent inductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex> between the inverter and the AC grid is realized, allowing the model control parameters to better match the actual system values. Moreover, by using a unity-cycle delay canceller, the duty cycle of the inverter is calculated one cycle ahead of time, which mitigates the delay between the actual and theoretical duty cycles caused by sampling and calculation delays. This further enhances the robustness of the control algorithm. In this paper, the proposed algorithm is simulated and compared with the advanced PIPR control method with a phase-locked loop. The simulation results verify that the proposed method is more efficient and superior.
Authors
- Kuncheng Li (ORCID: https://orcid.org/0000-0002-1898-3979)
- Shounian Deng (ORCID: https://orcid.org/0009-0000-9769-2469)
- Jia Zou
- Shuna Li
- Jianling Liao
Institutions
- China University of Mining and Technology (CN)
Publication Details
- Published
- 2024-11-22
- DOI
- https://doi.org/10.1109/ifeea64237.2024.10878773
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00