Enhancing K-Means Clustering Efficiency on FPGA: A Three-Design Approach to Parallel Implementation

The K-means clustering algorithm, which is widely used to find correlations between data in different application domains, is a suitable technique for clustring a data set into subsets of similar features. Due to the possibility of simple parallelization, this algorithm can be implemented in parallel on hardware such as FPGA, GPU, etc. to perform intensive calculations in a short period of time. However, the hardware resources available in parallel implementations are challenging for large-sized data. This paper introduces an efficient implementation of the K-means clustering algorithm on FPGA, aiming to reduce computational load and enhance performance for large-sized data sets. By dividing the search space into parts and designing specific hardware units for each part on the FPGA, the implementation optimizes the use of on-chip memory resources. Various implementations, including Custom IP_core, Microblaze, and a combination of both, are evaluated on the ML506 Virtex5 board. Results indicate that the Custom IP_core-based design outperforms other methods, showing higher calculation speed and lower resource consumption.