Repair of Resistive Open Defects on Word-Lines and Bit-Lines of SRAMs

Current rapid advancements in deep sub micron technologies have enabled the implementation of very large memory devices and embedded memories. However, the memory growth increases the number of defects, reducing the yield and reliability of such devices. Faulty cells are commonly repaired by using redundant cells, which are embedded in memory arrays by adding spare rows and columns. The repair process requires an efficient redundancy analysis (RA) algorithm. In previous repair algorithms (see [1]–[10]) with redundant rows and redundant columns nobody paid attention on the type of redundancy: if a fault was detected then it was repaired by an available redundant element - either row or column, no difference was seen between them. In this paper, the results of the investigation of realistic Resistive Open defects on the Word-lines (WL) and Bit-lines (BL) in the memory area of an SRAM instance are presented. Analysis showed that to successfully repair such kind of defects we must use row (respectively, column) redundant element for the repair of WL (respectively, BL) resistive open defect. The previous recommendation in repair algorithms, including the well-known CRESTA algorithm for the application of an available redundant row or column to repair any kind of defect/fault seems to be incorrect, in general.