Configurable DRAM Access for Neural Network Accelerators: A SystemC Virtual Platform Approach

With the advancement of integration technology, placing billions of transistors in embedded systems has become possible. This increase in the number of transistors has led to a rise in the processing power of these systems. However, memory manufacturing technology differs from that of processing systems, which has caused memory to lag in terms of latency and energy consumption compared to processing systems. This paper proposes an approach for optimizing the memory accesses of deep neural network accelerators. In this regard, we propose a flexible hardware solution that can access various types of 1D, 2D, 3D, and 4D data required for processing neural network layers. This versatility is significant as it allows the hardware to be used in a wide range of applications, contributing to performance optimization by calculating the optimized burst length of DRAM and reducing the number of off-chip DRAM accesses. A customized virtual platform is developed in SystemC for design space exploration. This platform builds a complete system model, including DRAM, the proposed hardware, the accelerator, and the RISC-V processor. Our simulation results show that the proposed hardware reduces DRAM access volume by up to 16% and decreases access time by up to 56%. These improvements are compared to the state-of-the-art SmartShuttle technique. The results are conducted across various layers with partitions similar to the SmartShuttle, and weight-stationary data flow. Additionally, in the input stationary data flow, the volume and time of off-chip memory access are reduced by up to 12% and 73%, respectively.