A Hierarchy of Machine Learning Processing Elements with Joint Micro Programmable Computation and Indexing

This paper introduces an embedded system featuring multiple microprogrammed configurable accelerators to implement massive computing in machine learning domain. These accelerators consist of Hierarchy of MicroProgrammed Configurable Architectures (H-iMPACs). Each H-iMPAC includes a microprogrammed computation unit and index generation units. By changing the microinstructions and using the flexibility of these microprogrammed units, various kernels such as one-dimensional and two-dimensional FFT/IFFT, matrix multiplication operations, etc. can be implemented. To illustrate the outperformance of our design, the proposed architecture is implemented on Xilinx Artix-7 FPGA. By evenly distributing computations among the H-iMPACs and utilizing a high-bandwidth Quasi Fat Tree (QFT) for inter communication, the calculations have become significantly faster compared to the initial version of this architecture (iMPAC). We also compare the implementation of a kernel (here a matrix multiplication and one-dimensional FFT) on this micro-programmable architecture with the same architecture that uses a hardwired controller. The results indicate exceedingly small penalty in terms of power consumption and required clock cycles compared to the architecture with hardwired controller.