Power Gating Switch Turn on Time Adjustment to Reduce Possible Impact in Power Integrity

With data rates rising and supply voltages falling in applications involving high-speed IOs, the requirement for more stable power integrity at the device, package and board has grown more crucial, as noise criteria have gotten even more stringent. On the other hand, the extensive use of power gating in modern microprocessors to reduce the power consumption of the chip is bringing in problems related to the high current spikes, which have bad effect on power integrity. The method shown in this paper intends to decrease current during switching on due to increasing time of switching, which provides us a lower impact on power integrity, so this will reduce the area of the decoupling capacitors and, because of this, the high-speed IO size can be reduced or, more importantly, this will make it possible to increase the number of work units, improve functionality.