Wafer map Anomaly Detection Driven by Contrast Learning and Vision Transformer Model

With the rapid development of the integrated circuit industry, wafers, as the carrier for chip manufacturing, have made their production efficiency and quality the focal point of industry attention. Therefore, timely anomaly detection on wafer maps holds significant importance. Wafer maps provide a visual representation of the test results of each die on the wafer and effectively present data along with its associated spatial information. Timely anomaly detection on these maps is crucial for enhancing product quality and production efficiency. This paper introduces an anomaly detection method for wafer maps that leverages the Vision Transformer (ViT) architecture and a contrastive learning mechanism. The ViT architecture is employed to deeply model the global information of wafer maps, followed by the use of a contrastive learning mechanism to capture key features that reflect healthy information in samples of healthy wafer maps. This method not only achieves leading performance but also demonstrates robust resilience under noisy and sample contamination conditions. This achievement provides strong support for the practical application of anomaly detection in wafer maps.