Physical-Design Aware Scan Cell Reordering for Low Power Testing

Scan chain architecture is widely employed in modern VLSI design for test applications. However, it often leads to high power consumption during testing. The architecture experiences elevated simultaneous switching activity due to non-functional input patterns applied during test time, resulting in significant peak power in the circuits. This increased power consumption can cause IR drop issues, negatively impacting the chip's yield. This paper proposes an innovative approach to reduce both peak power and routing length by effectively reordering the scan chains. Experimental results show that the proposed approach is effective for the ISCAS'89 and ITC'99 benchmark circuits and this method achieves lower peak power and routing length compared to the state of the art.