Deterministic Jitter Reduction Technique in Ultra High Speed Frequency Dividers

As the size of the transistor scales down rapidly, and a large number of transistors are integrated per unit area, this trend poses several design challenges in front of very-large scale integrated (VLSI) circuit and system designers. Various issues related to signal and power integrity come into picture at high-frequency operations, e.g., jitter, cross-talk, electromagnetic interference, etc. A technique for relative deterministic jitter (DJ) reduction in ultra-high speed frequency divider is proposed. Capacitance matching technique is realized to reduce the relative DJ caused by kickback from high-speed clock switching. The frequency of input clock is 16GHz, while the output clock is 8GHz. The simulations have been done for each transition edge of input clock and the results show that the relative DJ in worst case is reduced by 61% after capacitance matching.