SpikeSpec: An On-Chip Learning Neuromorphic Accelerator for Spectrum Sensing With Triplet-Boosting and Hardware Friendly Loss Function

Spectrum sensing (SS) is a pivotal function in next-generation (G) multiple-input-multiple-output (MIMO) communication systems, tasked with detecting and characterizing the occupancy or availability of frequency bands within the radio spectrum. Conventional SS techniques are hindered by challenges, such as hardware complexity and the signal-to-noise ratio (SNR) wall, leading to suboptimal performance in environments with high-noise levels. Recurrent neural networks (RNNs), particularly liquid state machines (LSMs), are highly effective for developing energy-efficient accelerators, as they efficiently capture temporal dependencies in primary user frequency spectrums with a reduced number of trainable parameters. This article introduces an innovative field programmable gate array (FPGA) accelerator based on LSMs, featuring fully integrated on-chip learning capabilities for SS. Our accelerator leverages reward-based spike timing-dependent plasticity (R-STDP) to discern temporal correlations within the related frequency band. Although traditional R-STDP methods face convergence difficulties during on-chip learning, the introduced approach overcomes this challenge with a novel, hardware-efficient loss function. This mechanism which is also hardware friendly, facilitates accelerated convergence with reduction of training period of about 46.67% in SS classification for hardware implementation. Moreover, we implemented a fully asynchronous, low-latency, unsupervised triplet-based spike-time-dependent-plasticity (STDP) learning mechanism in the LSM accelerator reservoir, which improves training accuracy by about 3.88% in high-noise channels while enhancing reconfigurability. Furthermore, we investigated various encoder mechanisms to identify the most efficient encoder architecture for our LSM, leading to an accuracy increase of 6.11%. Our optimized LSM architecture achieved 1.27 times and 2.01 times the LUT and register counts, respectively, compared to the basic fixed-reservoir LSM on the Virtex-707 FPGA.