Low Capacitance and Fast Response SCR for High-Speed I/O ESD Protections

A floating-base N-type transistor triggered silicon-controlled rectifier (FBNTSCR) device is developed for high-speed I/O electrostatic discharge (ESD) protection. The device, constructed by embedding a floating-base N-type transistor as the trigger element replacing the P-well tie in a standard SCR, enables the embedded bipolar to be avalanched at the collector-emitter breakdown voltage, providing a lower trigger voltage than the conventional LVTSCR. Furthermore, a lower parasitic capacitance is achieved by mitigating the capacitance associated with the N-well/P-well junction. The proposed design also has a shorter inherent SCR path, resulting in lower on-resistance, higher failure current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$l_{{t}{2}}$ </tex-math></inline-formula>) and lower overshoot voltage as well as faster turn on speed, all of which benefit the CDM ESD protection performance. Measurement results show the FBNTSCR has ~40.8% reduced trigger voltage, ~68.9% reduced parasitic capacitance and ~16.7% enhanced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$l_{{t}{2}}$ </tex-math></inline-formula> compared to the conventional LVTSCR.