High-Performance Enhancement-Mode GaN p-FET Fabricated With an Etch-Stop Process

The gate recess process for the enhancement-mode (E-mode) gallium nitride (GaN) p-FET is expected to create a high density of crystalline defects; thus, a large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\vert {V}_{\text {th}} \vert $ </tex-math></inline-formula> is often accompanied with a poor I<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>. To address this challenge, in this work, an etch-stop process is developed with a 1.5-nm AlN layer inserted in the p-GaN layer, so the dry-etch-based gate recess is terminated at the AlN layer. The AlN at the recess region is then removed using a wet etch, so the surface of the gate channel is shielded from the plasma bombardment during the dry etch. The fabricated etch-stop GaN p-FET demonstrates an E-mode operation with a large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {th}} = -4.9$ </tex-math></inline-formula> V, a high I<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> of 6.79 mA/mm, a small <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {th}}$ </tex-math></inline-formula> hysteresis of 0.2 V, and a high I<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>/I<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> ratio of 106. Furthermore, an E-mode n-channel FET was fabricated on the same epitaxial wafer to demonstrate the potential of the proposed etch-stop p-FET technology for GaN complementary logic (CL). Therefore, the technology demonstrated in this work is proved an effective approach to address the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {th}}$ </tex-math></inline-formula>–I<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> tradeoff in the GaN p-FET for CL applications.