A 43.4-dB Gain 7.6-mW 197.5% Bandwidth Double Noise-Canceling Cryogenic LNA Using Gain Peaking Technique for Multiple Spin Qubit Readout

This brief proposes a cryogenic stacked inverter-based gain-flattening low-noise amplifier (LNA) with dual current reuse and dual noise-canceling in 28-nm CMOS. The LNA features a current-reuse high-Q gate inductor and cascode inverter-based input stage with shunt-resistive feedback, optimizing wideband input impedance. A cryogenic aware self-body bias (SBB) mitigates <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm { th}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$r_{\mathrm { out}}$ </tex-math></inline-formula> variations at cryogenic temperatures. The design incorporates a source-degenerated common-source (CS) main amplifier, followed by current reuse inductor gain peaking cascode dual noise-canceling CS transistors, enhancing transconductance and suppressing noise in both main and auxiliary amplifiers. At cryogenic temperature (4 K), the LNA achieves a measured peak gain <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(S_{21})$ </tex-math></inline-formula> of 43.4 dB, with a large 3-dB bandwidth from 0.02 – 3.2 GHz (197.5% fractional BW) and a minimum NF of 0.37 dB (corresponding to noise temperature <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{N}$ </tex-math></inline-formula> of 25.8 K) at 0.7 GHz under power dissipation of 7.6 mW. The circuit occupies an active area of 0.31 mm2.