Gate Layout and Process Reliability Co‐Optimization in High‐Speed Vertical III–V Nanowire Metal‐Oxide‐Semiconductor Field‐Effect Transistor Technology

High‐speed vertical III–V nanowire transistors utilize their channel material for high frequency and low noise performance. A device layout revision to optimize gate resistance, in a trade‐off to gate‐source capacitance, is presented. A two‐step redesign of the established device layout is proposed. First step is demonstrated with fabricated structures. The second step predicts the design transition from double row gate fingers to wider array structures, motivated by numerical simulations. Distributed radio frequency modeling is used to assess the resulting input parasitic elements of the transistor. These design alterations also yield a potential for improved device process reliability. In parallel, this study analyzes sputtered tungsten used as the gate metal, focusing on measurements of its resistivity and variations in stress properties from different deposition conditions, thereby allowing further improved process reliability. It is found that 60 nanometer tungsten gate on a gate stack capped by a thin titanium nitride shows shifted stress properties compared to the same film deposited directly on the gate oxide. This work promises improved high‐speed process reliability as well as reduction of external gate parasitic elements by more than a factor of 2, what leads to increased gain and reduced noise figure at a given operating frequency.