Numerical Simulation on Stress on C4 Bump Distribution of Silicon Interposer

2.5D advanced packaging has become a major technological highlight in the development trend of semiconductor packaging from 2D to 3D. Various advanced CPUs/GPUs and high bandwidth memory (HBM) are integrated through 2.5D advanced packaging. The interconnection is achieved through the micro bumps of the chip and high-density BEOL layers on the frontside of the interposer, then by the through silicon vias (TSVs) connecting the upper and lower layers, and is finally soldered onto a traditional 2D packaging substrate through C4 (Controlled Collapsed Chip Connection) bumps. With the increasing demand for performance, 2.5D packaging requires more and more integrated chips with larger areas. There is a significant mismatch in the CTE (thermal expansion coefficient) between the silicon interposer and the substrate. Therefore, the effects will be significantly amplified, leading to reliability failure and even inability to proceed with the following packaging processes. Prospective finite element analysis (FEA) can be conducted on the shape and layout of C4 bumps to analyze their effect on mechanical stress buffering on the total package. Finally, based on these simulation results, the optimal combination is recommended so that the layout and shape of the C4 bumps can provide effective assistance for the overall stress buffering of the package.