Laser Assisted Bonding for Flip Chip Interconnection of Very Large Chips

In recent years, laser-assisted bonding (LAB) has emerged as a promising means to address specific flip-chip assembly issues associated with conventional mass-reflow (MR) and thermo-compression bonding (TCB) processes, for example chip warpage reduction. However, studies have predominantly focussed on small to medium sized chips. For memory, processor, and interposer applications, chip sizes may be much larger. The ability to effectively distribute laser energy across such larger interconnection areas is practically unexplored. This paper investigates LAB behavior for a 25mm x 26mm silicon chip comprising Cu pillar/SAC solder interconnects, with a particular focus on the size of the optically generated homogeneous laser beam. A heat transfer study was first conducted to estimate the relationship between chip surface temperature, which can be measured and controlled during the LAB process, and actual joint temperature, the latter requiring a special thermocouple assembly module. The responses allowed the determination of an appropriate range of LAB profile parameters for assembly development. Assembly results reported revealed that beam size extension beyond the chip region is critical to achieving repeatable defect-free interconnection of such large chips. This relationship was additionally supported by thermal finite element modelling (FEM) that demonstrated that the impact of convective effects at the chip periphery on solder joint temperature distribution, and remediation of same by beam size enlargement, became increasingly important with increasing chip size. It was further demonstrated that, despite the larger beam size and its effect on substrate surface temperature, post assembly chip warpage was reduced by about 50% using LAB as compared to the MR process. Finally, microstructural comparisons between LAB and MR validated that initial intermetallic compound (IMC) formations are significantly reduced on these large chip assemblies, in line with previous studies on smaller chips.