Development of High Density, Enhanced Reliability Wafer Level Packages

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to different failure modes like; cyclic fatigue induced solder joint cracking, package interconnect failure, silicon BEOL failure. Due to these reliability constraints WLP, are limited to relatively smaller sizes and less pin counts. This study investigates development of high pin count, high reliability WLP by ensuring chip package integration at all levels of interconnect; board to package, package to die and die BEOL. Package development was done with DOE variables like, multi-layer package routing, dielectric materials, solder alloys. Tradeoffs between different DOE variables must be achieved for overall package reliability improvement. Excellent reliability, functional performance, and chip package integration was achieved for highly integrated fan in and fan out wafer level packages.