Enabling High-density Heterogeneous Integration using Wafer-scale Chiplet Reconstitution Technology

As the demand for high-performance computing continues to grow, the integration of more and more chiplets into a package has become increasingly necessary. In this paper, we present a wafer-scale chiplet reconstitution technology that leverages low-temperature silicon dioxide to encapsulate a dense array of chiplets. To achieve high-density integration and ensure complete oxide encapsulation, a study is carried out to determine the minimum chiplet-to-chiplet gap that is required for a specified thickness of the chiplet. The study shows that a minimum ratio of ~ 1:2 (chiplet height: chiplet gap) is required to fill the gaps between the adjacent chiplets. Based on this observation, a test structure is designed consisting of a dense array of 150 μm x 150 μm passive chiplets that are 12 μm-thick with a chiplet-to-chiplet gap of 40 μm. The designed chiplet tier is fully encapsulated with 18 μm-thick low-temperature silicon dioxide. In addition, a compact circuit model for preliminary analysis of digital die-to-die signaling of the chiplet reconstitution technology is presented. The latency and energy dissipation of this model are evaluated using SPICE simulations.