Multi NoC Performance Driven Exploration on FPGA SoC for Industrial Applications

Field Programmable Gate Arrays (FPGAs) are pervasive everywhere, even more so in industrial and embedded domains. It provides support for diverse workloads with stringent latency requirements. In order to provide flexibility of programmable logic with power, performance and cost savings of hard IP, a Hard Processor System (HPS) along with FPGA fabric delivers reduced board space, system power and total cost of ownership savings by eliminating the requirement of a discrete embedded processor. This paper covers system level performance modeling of an HPS platform with multiple NoCs (Network-on-chip) , peripherals and memory hierarchy using Synopsys Platform Architect tool. As a case study, performance of Time Sensitive Networking (TSN) endpoints along with USB endpoints is thoroughly evaluated using concurrent traffic analysis. Our performance optimization results show 55% average latency reduction compared to baseline architecture. Early design space exploration allowed architectural optimizations impacting NoC silicon changes and sign off ≈ 8 months ahead of RTL (Register transfer level) define here verification start.