Trace Fusing Current Simulation in the Redistribution Layer of Wafer Level Packages

This paper uses fusing current data measured from experiments to develop and validate a simulation method in Ansys Mechanical 2022 R1 finite element analysis (FEA) to study fusing current in redistribution layer (RDL) traces on a silicon die. Fusing current was evaluated for several similar trace designs for a range of trace cross-sectional areas and lengths on multiple thicknesses of silicon. Resistances in the experiment were measured by a four-point measurement technique and compared with the nominal resistance over the temperature range as predicted from literature material properties. Two models were created to demonstrate the simulation approach. First, a model was made to test the fusing current for several lengths and diameters of wire in still air. The model showed only slight (<5%) variation between measured fusing current and simulated fusing current. This simple scenario gives confidence that the simulation approach is valid. Using the combination of transient heating of the wire from a ramped electric current with convection and radiation, the heat balance of the system can reliably simulate fusing current across a wider variety of systems when the surrounding thermal system is included in the model. The second model was a representation of the Wafer Level Chip Scale Package (WLCSP) with RDL on silicon. The trace geometry and system were modeled, and current was ramped over time across the circuit until the melting point of copper was reached and the trace was considered to have melted and fused. Some variations were observed between measurement and simulation, with thicker silicon showing more capacity to absorb the heating of the trace than in real-world measurements. Overall, simulation aligned well with measurements, with simulation results being between 4 to 14% of the measured fusing current value. The simulation approach appears appropriate to generalize to additional electronics packaging scenarios. Note that dielectrics

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Publication Details

Journal
IMAPSource Proceedings
Published
2025-02-10
DOI
https://doi.org/10.4071/001c.129615
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
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article

Trace Fusing Current Simulation in the Redistribution Layer of Wafer Level Packages

KyungRok Park, EunSook Sohn, Nathan Whitchurch, JiYeon Yoon et al.
IMAPSource Proceedings
Integrated Circuits and Semiconductor Failure Analysis
article

Trace Fusing Current Simulation in the Redistribution Layer of Wafer Level Packages

KyungRok Park, EunSook Sohn, Nathan Whitchurch, JiYeon Yoon, JeongMin Ju
article en

Abstract

This paper uses fusing current data measured from experiments to develop and validate a simulation method in Ansys Mechanical 2022 R1 finite element analysis (FEA) to study fusing current in redistribution layer (RDL) traces on a silicon die. Fusing current was evaluated for several similar trace designs for a range of trace cross-sectional areas and lengths on multiple thicknesses of silicon. Resistances in the experiment were measured by a four-point measurement technique and compared with the nominal resistance over the temperature range as predicted from literature material properties. Two models were created to demonstrate the simulation approach. First, a model was made to test the fusing current for several lengths and diameters of wire in still air. The model showed only slight (<5%) variation between measured fusing current and simulated fusing current. This simple scenario gives confidence that the simulation approach is valid. Using the combination of transient heating of the wire from a ramped electric current with convection and radiation, the heat balance of the system can reliably simulate fusing current across a wider variety of systems when the surrounding thermal system is included in the model. The second model was a representation of the Wafer Level Chip Scale Package (WLCSP) with RDL on silicon. The trace geometry and system were modeled, and current was ramped over time across the circuit until the melting point of copper was reached and the trace was considered to have melted and fused. Some variations were observed between measurement and simulation, with thicker silicon showing more capacity to absorb the heating of the trace than in real-world measurements. Overall, simulation aligned well with measurements, with simulation results being between 4 to 14% of the measured fusing current value. The simulation approach appears appropriate to generalize to additional electronics packaging scenarios. Note that dielectrics

IMAPSource ProceedingsVol. 2024(Symposium)
Amkor Technology (United States) (US)
Openalex Percentile: Top 98%
Integrated Circuits and Semiconductor Failure Analysis
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