Heterogeneous Integration Structure - FOSub for High End Product Substrate Development
This paper introduces an innovative new structure designed to achieve the highly growth of High speed computing (HPC), especially the application for Generative Artificial Intelligence (Generative AI) and Internet of things (IoT). In the ever-evolving landscape of Generative AI, advancements have been remarkable, albeit accompanied by a growing reliance on Graphics Processing Units (GPUs) and the significance of computational processing systems. Traditionally, both GPUs and CPUs have utilized Ball Grid Array (BGA) boards coupled with either Flip-Chip on Substrate (FOCoS) or Chip-on-Wafer-on-Substrate (CoWOS) packaging. These configurations involved the stacking of multiple layers of substrates to achieve the high speed computational performance. However, this paper presents a novel structure which combine both the Fan-Out Redistribution Layer (RDL) & substrate technology. This breakthrough not only marks a significant leap in the capabilities of substrate manufacturing processes but also enables the attainment of a remarkable line width and spacing of L/S=2/2um. The consequential advantages include reduction in processing time and a substantial enhancement in the overall yield of the manufacturing process. Also, the structure has a mainly improve by the Fan-Out technology, can connect the top die without silicon interposer, and different from the Flip-Chip on Substrate (FOCoS) structure with the solder free connection. Through the comparison of electrical simulations and actual samples, the study demonstrates that the performance of the new packaging structure is comparable to traditional 4-2-2L BGA boards, with no significant loss observed in the S21 parameter. Furthermore, by employing Fan-Out RDL technology, the number of substrate layers can be reduced, and compatibility with the 4-2-4L FOSub structure is achieved by utilizing Redistribution Layers (RDL) effectively. Encouragingly, reliability tests have been successfully passed, including PKG MSL3/TCT1000 cycle tests, further validating the reliability and stability of the new packaging structure.
Authors
- S.-G. Lee
- Yue Lin
- Wen Hung Huang
- Ming-Jian Huang (ORCID: https://orcid.org/0009-0003-3373-5468)
- Jen Kuang Fang
- Yan Wen Chung
Institutions
- Advanced Semiconductor Engineering (Taiwan) (TW)
Publication Details
- Journal
- IMAPSource Proceedings
- Published
- 2025-02-13
- DOI
- https://doi.org/10.4071/001c.129724
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00