Investigation for the Influences of Factors Within the Semi-Additive Process (SAP) on Nanovoid Formation in the Cu-Cu Interface by STEM Analysis

Electroless copper deposition is widely used in the electronics industry. In recent years, electronic components tend to be densified as the performance of electronic devices increases. The densification of electronics components means the decreasing of conductor width and spaces formed as the circuit patterns and reducing the diameter of Blind Via Holes used as an interconnect between the circuit layers within the electronic substrates. If voids exist in reduced diameter BVHs, the reliability of electronics components could decrease. Thus, voids formed in the electrolytic Cu / electroless Cu interface and electroless Cu / inner layer Cu interface and the cause of the formation of voids have been the focus of attention in recent years. Although there are some studies regarding voids formation in the interfaces of electrolytic Cu / electro-less Cu / inner layer Cu for such this reason, factors relating to the formation of nanovoids in the interfaces are not clearly mentioned. Therefore, the purpose of this paper is investigation for various factors that could cause void formation in the interface. Experiments performed on actual substrates consisting of copper foil, electroless copper layer, electrolytic copper layer and glass epoxy resin are very practical and easy to understand. On the other hand, it will be hard to find out the root cause of void formation owing to too complicated processes for production of these substrates. We adopted a special method of experiment to prepare samples in order to investigate the effect of just one factor from many factors. This method will be included in the process for preparing actual substrates for the formation of voids. STEM-EDX was used to confirm whether voids exist in the interface or not and the area of electroless copper layer is identified from EDX Ni-mapping results. AES also was used for analysis on surface of inner layer copper. The TEM lamellae were prepared with FIB. The results obtained from these experiments clarify that the formation of voids was related to the presence of copper oxide on the inner layer copper.

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Journal
IMAPSource Proceedings
Published
2025-02-10
DOI
https://doi.org/10.4071/001c.129621
Primary Topic
Additive Manufacturing Materials and Processes
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article
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article

Investigation for the Influences of Factors Within the Semi-Additive Process (SAP) on Nanovoid Formation in the Cu-Cu Interface by STEM Analysis

Kanji Matsumoto, Hisamitsu Yamamoto
IMAPSource Proceedings
Additive Manufacturing Materials and Processes
article

Investigation for the Influences of Factors Within the Semi-Additive Process (SAP) on Nanovoid Formation in the Cu-Cu Interface by STEM Analysis

Kanji Matsumoto, Hisamitsu Yamamoto
article en

Abstract

Electroless copper deposition is widely used in the electronics industry. In recent years, electronic components tend to be densified as the performance of electronic devices increases. The densification of electronics components means the decreasing of conductor width and spaces formed as the circuit patterns and reducing the diameter of Blind Via Holes used as an interconnect between the circuit layers within the electronic substrates. If voids exist in reduced diameter BVHs, the reliability of electronics components could decrease. Thus, voids formed in the electrolytic Cu / electroless Cu interface and electroless Cu / inner layer Cu interface and the cause of the formation of voids have been the focus of attention in recent years. Although there are some studies regarding voids formation in the interfaces of electrolytic Cu / electro-less Cu / inner layer Cu for such this reason, factors relating to the formation of nanovoids in the interfaces are not clearly mentioned. Therefore, the purpose of this paper is investigation for various factors that could cause void formation in the interface. Experiments performed on actual substrates consisting of copper foil, electroless copper layer, electrolytic copper layer and glass epoxy resin are very practical and easy to understand. On the other hand, it will be hard to find out the root cause of void formation owing to too complicated processes for production of these substrates. We adopted a special method of experiment to prepare samples in order to investigate the effect of just one factor from many factors. This method will be included in the process for preparing actual substrates for the formation of voids. STEM-EDX was used to confirm whether voids exist in the interface or not and the area of electroless copper layer is identified from EDX Ni-mapping results. AES also was used for analysis on surface of inner layer copper. The TEM lamellae were prepared with FIB. The results obtained from these experiments clarify that the formation of voids was related to the presence of copper oxide on the inner layer copper.

IMAPSource ProceedingsVol. 2024(Symposium)
Nomura Research Institute (JP)
Openalex Percentile: Top 97%
Additive Manufacturing Materials and Processes
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