Using FEM Simulation to Predict the Mechanical and Thermal Performance of FO-EB-T Package

In order to solve the problems that high price and low process yield of single multi-functional large-size chip, homogeneous and heterogeneous integration has become the trend of modern high-end packaging technology due to faster signal transmission speed and also a benefit for space management. According to that, the development of chiplet advanced packaging technology is particularly important. During the chiplet packaging process, many structural mechanical warping problems may be encountered. In addition to the difficulty of the process, the accompanying challenges also have more severe thermal problems. Take server for example, The Thermal Design Power (TDP) of the server is increasing year by year. It can basically reach more than 500W per package. Above that, before the overall packaging is completed, the reliability issue and thermal problem must also be taken into consideration. So the selection and matching of packaging materials need to be carefully selected, including organic interposer, heat sink, adhesive, etc. The Fan-Out Embedded Bridge with TSV (FO-EB-T) structure is taken to be the test vehicle in this paper. The assembly process of chiplet integration is firstly studied for wafer warpage in silicon bridge die with TSV connection process, pre-molding, u-pad, die bonding, underfill, molding process and C4 bump process. The glass carrier and organic compound candidates are predicted to make the wafer warpage within the criteria of each process and also show good alignment with experimental data. Simultaneously, the package warpage investigation is checked by the best combination of organic compound selection. Finally, the overall reliability and thermal performance is simulated through structure and material parametric simulation such as heat sink type and core type. Overall, this paper proposes the simulation method to predict both in-process warpage and reliability stress performance and also take thermal performance into considered. Besides, the metrology of in-process warpage prediction will be explained which suffers the saddle shape warping performance. Above that, the FO-EB-T package development that can save the DOE and reduce the warpage and stress risk is been proposed.

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Publication Details

Journal
IMAPSource Proceedings
Published
2025-02-13
DOI
https://doi.org/10.4071/001c.129749
Citations
2
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
1.46
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article

Using FEM Simulation to Predict the Mechanical and Thermal Performance of FO-EB-T Package

Vito Lin, Shane Lin, Teny Shih, Y.P. Wang et al.
2 citations
IMAPSource Proceedings
3D IC and TSV technologies
1.46
article

Using FEM Simulation to Predict the Mechanical and Thermal Performance of FO-EB-T Package

Vito Lin, Shane Lin, Teny Shih, Y.P. Wang, Andrew H. Kang
article en
2 citations

Abstract

In order to solve the problems that high price and low process yield of single multi-functional large-size chip, homogeneous and heterogeneous integration has become the trend of modern high-end packaging technology due to faster signal transmission speed and also a benefit for space management. According to that, the development of chiplet advanced packaging technology is particularly important. During the chiplet packaging process, many structural mechanical warping problems may be encountered. In addition to the difficulty of the process, the accompanying challenges also have more severe thermal problems. Take server for example, The Thermal Design Power (TDP) of the server is increasing year by year. It can basically reach more than 500W per package. Above that, before the overall packaging is completed, the reliability issue and thermal problem must also be taken into consideration. So the selection and matching of packaging materials need to be carefully selected, including organic interposer, heat sink, adhesive, etc. The Fan-Out Embedded Bridge with TSV (FO-EB-T) structure is taken to be the test vehicle in this paper. The assembly process of chiplet integration is firstly studied for wafer warpage in silicon bridge die with TSV connection process, pre-molding, u-pad, die bonding, underfill, molding process and C4 bump process. The glass carrier and organic compound candidates are predicted to make the wafer warpage within the criteria of each process and also show good alignment with experimental data. Simultaneously, the package warpage investigation is checked by the best combination of organic compound selection. Finally, the overall reliability and thermal performance is simulated through structure and material parametric simulation such as heat sink type and core type. Overall, this paper proposes the simulation method to predict both in-process warpage and reliability stress performance and also take thermal performance into considered. Besides, the metrology of in-process warpage prediction will be explained which suffers the saddle shape warping performance. Above that, the FO-EB-T package development that can save the DOE and reduce the warpage and stress risk is been proposed.

IMAPSource ProceedingsVol. 2024(Symposium)
Siliconware Precision Industries (Taiwan) (TW)
Openalex Percentile: Top 19%
3D IC and TSV technologies
1.46
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