A Novel High Resolution Dry Film Photo-Imageable Dielectric for Redistribution Layer in Advanced Packaging Applications

To meet the needs for finer pitch redistribution layer (RDL) designs on organic, glass and silicon interposers, substrates, and panels, a photoimageable dielectric (PID) dry film (DF) has been developed suitable for embedded trace dual damascene processes. This high-resolution, dry film PID is based on the aqueous developable benzocyclobutene (AD-BCB) platform already used in HVM production for redistribution layer patterning in advanced packaging. The PID is negative tone, tetramethylammonium hydroxide (TMAH) developable with a Dk of <2.9 and cure temperature of 220°C. Dry film rolls have been successfully made at pilot scale with film thickness ranging from 5μm to 45μm and is able to achieve a 2:1 aspect ratio for 10μm and 20μm films. Patterning has been demonstrated on i-line stepper, mask aligner and laser direct imaging (LDI) tools. Using a 2-stage vacuum laminator, this PID achieves excellent planarity over plated metal contacts and lines. Cured films have passed bias HAST testing (130°C, 85% RH, 96hr, 5V) with line space patterning of 13 μm and 9 μm with no delamination or copper dendrite formation. Two-layer lithography, reactive ion etch (RIE) surface treatment and the Ti/Cu sputter process have been optimized to achieve high resolution patterning with copper peel strength of ≥0.4kgf/cm after HAST (130°C, 85% RH, 96hr) for a 25μm electroplated copper layer. Moreover, the cured dry film has low shrinkage during cure, robust chemical resistance and no leaching in copper plating baths. Based on these attributes, the material demonstrates suitability for 2.5D and 3D advanced heterogeneous chiplet integration schemes including Fan-Out Wafer and Panel Level processing (FO-WLP, FO-PLP).

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Publication Details

Journal
IMAPSource Proceedings
Published
2025-02-13
DOI
https://doi.org/10.4071/001c.129754
Citations
1
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
0.73
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article

A Novel High Resolution Dry Film Photo-Imageable Dielectric for Redistribution Layer in Advanced Packaging Applications

Lu Zhou, Gregory Prokopowicz, Colin O. Hayes, Michael Gallagher et al.
1 citations
IMAPSource Proceedings
3D IC and TSV technologies
0.73
article

A Novel High Resolution Dry Film Photo-Imageable Dielectric for Redistribution Layer in Advanced Packaging Applications

Lu Zhou, Gregory Prokopowicz, Colin O. Hayes, Michael Gallagher, Mark Reynolds, Kevin Wang, Yaming Jiang, C. J. Gilmore, Andrew Lotz
article en
1 citations

Abstract

To meet the needs for finer pitch redistribution layer (RDL) designs on organic, glass and silicon interposers, substrates, and panels, a photoimageable dielectric (PID) dry film (DF) has been developed suitable for embedded trace dual damascene processes. This high-resolution, dry film PID is based on the aqueous developable benzocyclobutene (AD-BCB) platform already used in HVM production for redistribution layer patterning in advanced packaging. The PID is negative tone, tetramethylammonium hydroxide (TMAH) developable with a Dk of <2.9 and cure temperature of 220°C. Dry film rolls have been successfully made at pilot scale with film thickness ranging from 5μm to 45μm and is able to achieve a 2:1 aspect ratio for 10μm and 20μm films. Patterning has been demonstrated on i-line stepper, mask aligner and laser direct imaging (LDI) tools. Using a 2-stage vacuum laminator, this PID achieves excellent planarity over plated metal contacts and lines. Cured films have passed bias HAST testing (130°C, 85% RH, 96hr, 5V) with line space patterning of 13 μm and 9 μm with no delamination or copper dendrite formation. Two-layer lithography, reactive ion etch (RIE) surface treatment and the Ti/Cu sputter process have been optimized to achieve high resolution patterning with copper peel strength of ≥0.4kgf/cm after HAST (130°C, 85% RH, 96hr) for a 25μm electroplated copper layer. Moreover, the cured dry film has low shrinkage during cure, robust chemical resistance and no leaching in copper plating baths. Based on these attributes, the material demonstrates suitability for 2.5D and 3D advanced heterogeneous chiplet integration schemes including Fan-Out Wafer and Panel Level processing (FO-WLP, FO-PLP).

IMAPSource ProceedingsVol. 2024(Symposium)
DuPont (United States) (US)
Openalex Percentile: Top 31%
3D IC and TSV technologies
0.73
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