Megachip: An Advanced Packaging Solution for Chiplet Integration

We present our development of a novel heterogeneous chip-tiling approach that enables the realization of extremely large-area integrated circuits (ELAICs) or “Megachips”- containing tens of closely spaced small chiplets that are interconnected via redistribution layers (RDLs) fabricated using a lithographic process on top of the tiled chiplets. The concept of the Megachip approach is to interconnect small specialized chiplets, into a large, single-chip-like monolithic integrated circuit. Multiple heterogeneous chiplets can be interconnected within layers that redistribute, or reroute, the electrical inputs and outputs (I/O) to enable chiplet-to-chiplet (C2C) communication. This architecture relies on chip-like electrical traces having narrow line width (~1-2 μm) and close C2C spacing (~5-20 μm) to achieve high I/O density, high bandwidth, and low-latency circuits. A Megachip has a chip-like silicon content (about 99%), allowing highly stable and inexpensive fabrication of a heterogeneous system-on-chip with chip-like wiring densities. Megachip tiling with mix-and-match die is well suited to meet the high-end electronics requirement of smaller form factors, higher performance, and increased packaging flexibility.