Fan-Out Embedded Bridge with TSV (FO-EB-T) Package Solution for Enhancing HPC Application

No one can deny we are definitely in Artificial Intelligence (AI) generation as it’s now immersing in all the necessities of our daily life, which effect and become every single part of our behavior. By accelerating the development of leading-edge assembly package combine with new generation high-bandwidth memory (HBM) that the speed can be even increased to 8Gbps, a much higher efficient AI chip can be achieved in enhancing the high-performance computing (HPC) application. Assembly of Fan-Out Embedded Bridge (FO-EB) chiplet package adopts organic interposer with embedding bridge die which can be aggressively replaced by silicon bridge die with through-silicon-via (TSV) technology to be named as FO-EB-T. This 3D packaging removes the silicon interposer with the benefit of cost effectiveness and directly connects chips with different functions in the form of TSV. The high performance accommodates reducing package height, enhancing design flexibility, shortening the chip transmission path to reinforce chip operation speed. Besides, in order to effectively integrate different functions and process chips to meet the needs of high computing power, low latency, and low power consumption for Server AI computing, Self-driving cars, Networking etc., not only to breakthrough in packaging technology, but the methods of connecting chips and even the material used to connect will be the focus of technology development. In this paper, the selectivity study in terms of the interface connection is covered in pathfinding. The workability with integrated passive device (IPD) added was evaluated to verify the electrical voltage stabilization for package of FO-EB with TSV. Also, the module bonding on substrate method requirement for large Chip Module (CM) was studied as well.