Panel-level Fan-out: Relationship Between Panel Size and Cost Reduction

Panel-level fan-out packaging is a growing segment of the packaging industry. Some analysts expect that 7% of fan-out packages will be built with panel-level fan-out technology by 2025. The key reason for designers to consider a change from wafer-level to panel-level fan-out is cost reduction. Most activities for fan-out packaging are batch activities performed on the entire wafer or panel at one time. The more die processed during batch activities, the greater opportunity for cost reduction. Although this economic concept is simple, the reality of implementation is complicated. Handling wafer warpage and die shift can be a challenge even at the wafer level; these must be considered at the panel level as well. There are a few panel sizes available, and using the largest panel size for economic advantage may involve a trade-off with yield. New equipment or materials may be required, so capital expenditure should be considered as well. It is one thing to recognize the potential cost advantage of producing more chips at once, but designers and fabricators must understand whether to expect a 5% or 50% cost reduction. This paper will analyze the cost of multiple designs built using wafer-level fan-out with a 300mm wafer, and panel-level fan-out using a 515x510mm panel and a 600x600mm panel. Key assumptions, such as package size and yield, will be tested to evaluate their impact on cost reduction. The goal of this paper is to analyze the cost reduction that can be reasonably expected when moving from wafer-level to panel-level fan-out.