Optimizing Chiplet Disaggregation with Package Technology

As the chiplet concept is making its way into products, some are declaring a “chiplet revolution” in the semiconductor industry. The term revolution is used because of the paradigm shift from large, monolithic “System on Chips (SoC’s) to thoughtful disaggregation of chips into functional parts, or “chiplets,” requiring packaging of these “chiplets” in a cost-effective packaging technology. Multi-chip packaging has been in use for decades for various forms of heterogeneous integration. Now, the movement is spurred largely by the slowing of Moore’s law and the need to accelerate performance by methods other than semiconductor node progression. High-performance requirements are pushing the core processor to more advanced technology nodes, while other functions such as analog interfaces and memory are better served by different technologies, resulting in a need for heterogeneous integration of various “chiplets” in a single package. For example, customers may still require 5-volt interfaces and Analog-to-Digital Converters (ADCs) which are not possible in smaller geometries. On the other side, contemporary trends on communication like 10BaseT1S require upgrades of existing Microcontroller Units (MCUs). In general, this breaks down into three distinct types of chiplets: computing, interfaces (including analog and networking) and memory. Each of these have different interface bandwidth requirements and ideal technologies. Efforts are underway in the industry to develop standards that are optimized for bandwidth, latency, and power. However, the standardization and interoperability requirements will likely add some overhead in these areas. It is speculated by some that this concept may lead to some semiconductor Intellectual Property (IP) being “commodified” similar to what happened to some memory technologies in the past. Industry-wide standards can also create synergy for evolving and improving of the interfaces, contributing to the overall value of advanced packaging. Historically considered a “necessity” to connect chip power and signals, packaging now brings more value to the system solution. As Input/Output (I/O) density and bandwidth increase, so does package cost. The key is to “right-size” technology to meet bandwidth and cost targets. Disaggregation of large multi-core devices likely require thousands of connections and no latency impact, while implementation of an I/O hub or analog interface may require tens or hundreds of connections and can possibly afford some increased latency. Clock synchronization and error correction are other considerations that contribute to area and latency. As a SoC is disaggregated into chiplets, the SOC signals and connections to the on-chip communication bus are analyzed for mapping to a chiplet interface. In some cases, a standard interface may be the best solution. In other cases, a custom interface may be most suitable for power, area, and latency requirements. The bandwidth, latency, power, and area requirements are assessed to determine the interface requirements and packaging technology required to meet specifications.