Using a Novel Co-Design Prototyping Approach for System-in-Package Devices

System technology co-design (STCO) is the critical process of optimizing the interface between integrated IC device(s), package, and printed circuit board (PCB) at the early stages of product design and development. STCO can avoid poor system planning which could otherwise impact cost, yield, and performance. This paper focuses on the challenges and opportunities of STCO for system-in-package (SiP) and multi-chip package (MCP) solutions, which use a combination of wire bond and flip-chip die as well as SMT (surface mount technology) passive components. A scalable methodology is presented that uses Xpedition Substrate Integrator, a software tool for single-die ASIC and 2.5/3D packaging that automates the optimization of the system-level netlist, to achieve robust floorplanning and connectivity efficiency for SiP co-design. Compared to manual methods, this specialized workflow on typical SiP designs reduced up to 10-14% decrease in net congestions, leading to improvements in form factor, cycle time, and performance.